Variable Delay Line
Original Publication Date: 1979-Jun-01
Included in the Prior Art Database: 2005-Feb-20
In known systems, a fixed delay line can be made with a shift register of the required length. A variable delay is often accomplished by changing the speed on a charge-coupled device (CCD) shift register in order to have the correct delay. This requires a variable clock. An alternative for digital data is to write into one random-access memory while reading the information from another random-access memory at the same address. The address can come from a counter which is incremented until the desired delay has been achieved. Then the read/write select is switched between the two memories, the counter reset, and the process repeated. This method needs twice as much memory as the maximum desired delay. Below is described hardware which needs at most one bit more memory than the maximum delay.