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Logic Block Hardware Reduction

IP.com Disclosure Number: IPCOM000067245D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Reddi, UP [+details]

Abstract

It is well known that the amount of hardware used to implement logic circuits can be reduced if the Boolean expressions describing the logic are minimized. A standard method of minimization is by tabular-lookup in truth tables, considering every possible input combination. Since the number of input combinations for a binary logic function increases as 2/N/ for N inputs, such minimization quickly becomes impractical. However, by changing the notation in the Boolean expression to that of mathematical functions, and then applying various logical equivalences or simplification algorithms, a rapid and simple approach to hardware minimization is achieved. Also, this approach is amenable to automation.