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This address input true/complement generator and decoder circuit enables faster decoding time for memory components using transistor transistor logic (TTL) inputs.
English (United States)
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Memory Address Input And Decoder Circuit
This address input true/complement generator and decoder circuit enables
faster decoding time for memory components using transistor transistor logic
During standby, restore pulse R is high, and chip select CS and delayed chip
select DCS are low. Voltage nodes T, C and B are restored to the lower of V or
R-Vt. Voltage node A and word line WL are held to ground potential. During an
access cycle, CS is brought high and R falls to ground. Depending upon whether
address input SA is high or low, either the true output T or the complement
output C of the true/ complement generator of Fig. 1 is discharged to ground,
either through T2 to the inputs A or through T5 and T6.
If any of the Address T/C inputs coupled to a particular decoder circuit (Fig. 2) remain high, nodes A and B will be discharged through T8 and one or more of
devices T7. After a sufficient delay to allow the discharge of node B, DCS rises
to VH, but since the gate of T10 has been discharged, word line WL remains low.
If all of the Address T/C inputs to a decoder are discharged, nodes A and B
remain charged and allow DCS to drive WL to its selected state.
Nodes R, B, T and C should all have levels as high as possible, and the up
level of CS should be less than the up level of SA + Vt for proper operation.
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