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Time Delay Circuit Disclosure Number: IPCOM000067287D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20

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Incerto, RJ [+details]


In high performance machine designs, many logic paths require a minimum delay to eliminate large delay skews between long and short logic paths. Emitter-coupled logic (ECL) circuits operate with subnanosecond delays; therefore, many logic gates may be required to pad the short paths. This circuit provides a large delay time using a single ECL circuit. A 10X increase in delay is typical.