Time Delay Circuit
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20
In high performance machine designs, many logic paths require a minimum delay to eliminate large delay skews between long and short logic paths. Emitter-coupled logic (ECL) circuits operate with subnanosecond delays; therefore, many logic gates may be required to pad the short paths. This circuit provides a large delay time using a single ECL circuit. A 10X increase in delay is typical.