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Processor To Processor Final Communication

IP.com Disclosure Number: IPCOM000067315D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
MacSorley, OL [+details]

Abstract

The figure shows a system including two processors A and B. Each processor has its own I/O bus 11, 12 and a plurality of devices 25-28 attached by dedicated device adapters 21-24. In order to provide interprocessor communication, a common I/O bus 31 is provided. Common I/O bus 31 is connected to each of the processor I/O buses by primary bus adapters 33, 34. In addition to the devices directly attached to each processor I/O bus 11, 12, a plurality of I/O devices shared in common between all processors are connected to the common I/O bus by one or more secondary bus adapters 41. Each of the secondary bus adapters has a secondary I/O bus 43 to which common device adapters 45, 47 may be connected. Each of these common device adapters may be accessed by any one of the processors.