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Dynamic Double-Bit Partitioner

IP.com Disclosure Number: IPCOM000067319D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Jensen, BH Rugila, G [+details]

Abstract

This dynamic double-bit partitioner circuit generates dynamically four outputs and is capable of driving substantial capacitive loads with low DC power. This circuit requires no inverters to generate the inverse of the two inputs A and B as does the standard partitioner, rather it uses its own internal nodes as inputs to the next stages.