Virtual Address Translation Apparatus
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20
Computer systems utilizing virtual addressing require logic circuitry for supporting the translation of the virtual address and the handling of the address after the translation has been performed. Advantage can be taken of the fact that once a virtual address has been translated, that if both the virtual address space and the main storage space are divided into pages of equal size, the byte identifier can be incremented or decremented within the same page without the need for further translation. Further, for those addresses where the virtual address equals the real address the common page size permits incrementing and decrementing of the address without the need for further translation unless a segment boundary is crossed, and that is a violation.