Browse Prior Art Database

Microprocessor Interrupt System Extension

IP.com Disclosure Number: IPCOM000067360D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Aakre, DE Buesing, DA Ziecina, FJ [+details]

Abstract

In some instances, mircoprocessors for controlling I/O devices in a computer system may have only one interrupt level. Some I/O devices, such as a multifunction I/O device which can read, punch and stack unit record cards, require the controller to quickly process many interrupts. The interrupt circuit shown in Fig. 1 facilitates the handling of multiple interrupts on a single interrupt level of an I/O controller (IOC) of the type shown and described in the IBM Technical Disclosure Bulletin 20, 5294-5297 (May 1978). The circuit of Fig. 1 permits each of several independent microcode segments to each have a set of interrupts associated with it, and these interrupts are maskable under program control.