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Pad Layout For Large-Scale Integrated Device

IP.com Disclosure Number: IPCOM000067387D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Moth, FT [+details]

Abstract

Large-scale integrated circuits formed on a silicon wafer can include a number of different circuit portions, each of which is repeated in different areas of the circuit. These portions are known as "macros". Each of them is formed by photolithographic techniques from a corresponding unique mask, the image of which is stepped across the wafer to define the macro in various locations. To minimize the cost of a circuit, it is desirable to keep the number of macros to a minimum.