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Partitioned Memory And Split SCE For Asymmetric Multi-Processor

IP.com Disclosure Number: IPCOM000067407D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Wilson, MW [+details]

Abstract

Fig. 1 is a computer organization consisting of a main storage or memory 2, a storage control element (SCE) 4 and two processing elements (PEs) 6 (engine A) and 8 (engine B). Main storage 2 is assumed to be partitioned by an electronic fence 10 into two logical (and physical) parts, namely an addressable main store 12 and a system Q area 14. The latter area may not be addressed explicitly by generation of a resolved address by any instruction on a processor. It may be addressed implicitly by an instruction (which implies that during the execution phase of the instruction, access to Q area contents can be made by the PE hardware). The former area, addressable main store, contains user and system program and data. The Q area contains "control" data for the system.