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Chip Design Disclosure Number: IPCOM000067432D
Original Publication Date: 1979-Aug-01
Included in the Prior Art Database: 2005-Feb-20

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Dunn, EC Elliott, JR Fraim, NR Whitehill, JW Williams, TW [+details]


Described herein is a memory element chip suitable for use with MSI (medium scale integration) modules. As shown in the figure, the chip includes a plurality of shift register latches (SLR) partitioned into four pairs of SRLs. Each pair of SRLs is fitted with input data lines and a scan line for performing tests. Each pair of SRLs is further supplied with an independent clocking tree. There are two pairs of phase-hold latches and two pairs of set/reset latches. The L-2 portions of all eight latches are the hazard-free latches. The L-1 and L-2 portions of each latch are provided as outputs to the chip I/Os.