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The use of a "holding level" in conjunction with the appropriate compensation on a peak detector extends the useful operating range of the peak detector on semi-repetitive signals.
English (United States)
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Peak Detector For High Speed Semi-Repetitive Voltage Peaks
The use of a "holding level" in conjunction with the appropriate
compensation on a peak detector extends the useful operating range of the peak
detector on semi-repetitive signals.
The storage capacitor C1 is initially discharged through resistor R3, which is
then disconnected from the capacitor.
The buffer amplifier Z3 is a voltage follower so that its output is always equal
to the voltage stored on capacitor C1, thereby providing the output and feedback
voltage without loading down the capacitor C1. Resistors R6 and R7 are used to
divide the capacitor voltage to provide a holding level reference at the input of
Z4. Here R7 has been chosen to be 100 x R6, so that the "holding" reference is
approximately 99% of the capacitor voltage.
Transistor Q1 conducts Z3's bias current away from the storage capacitor to
minimize the drift of the stored voltage. The other unit of bias current flowing
through R4 is provided directly by Z2. Capacitor C2 is connected between the
base and emitter of Ql for stability.
A semi-repetitive input signal is applied through Rl to the input of Z1. If the
input signal is greater than the "holding" level reference present on the Z4 +
input, then the output of Z4 will slew in the negative direction to reverse bias D3.
This process continues until diode D4 becomes forward biased through resistor
R8. At this time, the "holding" level amplifier has isolated itself, and the full input
signal will be applied to Z1.
If the + input of Z1 is more positive than the voltage stored on capacitor C1
(as fed back through amplifier Z3 and resistor R2 to Z1), then the output of Z1
will slew in the positive direction to forward bia...