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Parity Predict For Three-Input Logical Operations

IP.com Disclosure Number: IPCOM000067537D
Original Publication Date: 1979-Aug-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Olin, KE Weinberger, A [+details]

Abstract

The described logic produces an updated parity predict signal which is a function of the input data for a three-input adder as well as of the input parity bits, so that an input parity error, which manifests itself in a byte of input data having a wrong parity bit, propagates into an output parity error. Let XOR = control signal specifying the logical operation exclusive-OR AND = control signal specifying the logical operation AND. OR = control signal specifying the logical operation OR. where XOR, AND, OR are mutually-exclusive. (AO,...,A7, PA) = byte of input data A with parity bit PA. (BO,...,B7, PB) = byte of input data B with parity bit PB. (CO,...,C7, PC) = byte of input data C with parity bit P .