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Self-Aligned, Uncompensated, Shallow Emitter Implant Technique

IP.com Disclosure Number: IPCOM000067695D
Original Publication Date: 1979-Sep-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Lee, CH [+details]

Abstract

An ion implant technique is described for fabrication of a self aligned uncompensated and shallow junction emitter for a transistor with horizontally graded base doping near the emitter window edge. The technique can provide an emitter junction of low leakage and low capacitance. The tunneling leakage component from the emitter junction can be completely eliminated, if desired. The process does not need a base photoresist step. The emitter region defects can be minimized. The yield of the transistor is expected to increase.