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Low Temperature Recessed Oxide Isolation Oxidation Disclosure Number: IPCOM000067701D
Original Publication Date: 1979-Sep-01
Included in the Prior Art Database: 2005-Feb-20

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Lee, CH Vesely, AF [+details]


The concept of electrically isolating devices on a semiconductor wafer with an annular silicon dioxide ring which surrounds the device is well known and has been described in U.S. Patent 3,648,125. In forming the silicon dioxide isolation, the substrate is masked with an oxidation resistant layer, openings made in the mask, and the wafer exposed to a vapor and oxygen atmosphere while heated to a temperature on the order of 1,000 degrees C for several hours. Unfortunately this ure high temperature oxidation step drives impurity regions in the device outwardly as, for example, a subcollector region. This outward extension of the impurity region can ultimately reduce the yield of the transistor fabricated in the isolated region, and generally decreases the breakdown voltage of the collector junction.