Browse Prior Art Database

Edge-Sensitive LSSD Circuit

IP.com Disclosure Number: IPCOM000067721D
Original Publication Date: 1979-Sep-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Saunders, LF [+details]

Abstract

Circuitry is provided for detecting non-LSSD logic signal transitions in level sensitive scan design (LSSD) logic networks. LSSD logic networks are of the type described in U.S. Patent 3,806,891 and find utility in computer systems. There are, however, requirements in computer systems, such as in the case of generating interrupts, for generating a single LSSD compatible pulse per transition of non-LSSD data. The logic circuitry for such functions should remain in an idle state as long as the input is inactive, go to an output state when the input switches to the active state, and then switch to a wait state until the input returns to an active state.