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Save And Restore CPU Status Disclosure Number: IPCOM000067722D
Original Publication Date: 1979-Sep-01
Included in the Prior Art Database: 2005-Feb-20

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Crowley, RD Kempke, WG [+details]


An arrangement is provided in a computer system where during a branch and link operation a local storage link register is loaded with status at the same time the link address is stored. This is possible because the link address has fewer bits than the capacity of the local storage register, and the address for the return does not include the two low order bits because these bits are forced to a particular state. Hence, with a 16-bit local storage register it is possible to include four status bits because only 12 address bits must be saved. In the past during a branch and link operation the status of the central processing unit (CPU) was saved either in a hardware register or in a local storage array, but when saved in a local storage array, additional machine cycles were required for accessing the array.