Browse Prior Art Database

Exception Condition Sequencer

IP.com Disclosure Number: IPCOM000067726D
Original Publication Date: 1979-Sep-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Helvig, JD Lawlor, FD Ranweiler, JG [+details]

Abstract

The operation of most conventional computers is controlled by a sequence of programmed instructions. For most programming above the horizontal microcode (HMC) level, the instruction sequence is generally sequential; that is, executed in the order in which the instruction sequence appears in storage. The sequencing mechanism for this is fairly simple. The current instruction address, which resides in an instruction address register (IAR), is added to the instruction length, which is architecturally defined by an instruction length code (ILC), to obtain the address of the next sequential instruction (NSI).