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High Performance FET Process Using Deep Dielectric Isolation And High Conductivity Silicides

IP.com Disclosure Number: IPCOM000067754D
Original Publication Date: 1979-Sep-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Crowder, BL [+details]

Abstract

The use of deep trench isolation avoids the problems of "pinching" and "birds beak" associated with Si(3) N(4) oxidation masking, and also allows for a thicker isolation oxide. A second advantage is that the surface is nearly planar prior to depositing the layers used for interconnection and for gate electrodes. The n regions serve only to connect the devices to the silicide/polysilicon rails. These regions may be defined by ion implantation or by outdiffusion from the doped polysilicon in the composite interconnection. At present, both the gate electrode and the interconnection replacement for diffusions can be made less than 2 ohms/square. The structure is shown in Fig. 1 in three views.