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This technique provides a method of increasing the module circuit density on multi-chip modules by reducing the area required for error correction pads. This leads to a lower cost system.
English (United States)
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Error Correction Technique
This technique provides a method of increasing the module circuit density on
multi-chip modules by reducing the area required for error correction pads. This
leads to a lower cost system.
Cost optimization studies indicate that cost advantages at the system level
can only be obtained if increased circuit density is achieved at the module and
board level commensurate with increasing semiconductor chip integration levels.
The cost per circuit at the chip level is higher, for given ground rule dimensions,
for a higher level of integration at the chip level. Thus, to realize the benefit of
higher chip integration level, an increase in circuit density at the module and
board level is necessary so that cost savings can be realized through a reduction
in module and board cost to off-set the increase in cost per circuit at the chip
level. It has been proposed that each I/O device pad be connected to an error
correction pad on the substrate. With the present and future high degree of
integration where each chip has many I/O pads, the space provided for the error
correction pads becomes significant and increases the cost of the package.
In this technique fewer error correction pads would be provided, thereby
saving space on the substrate. The number of error correction pads provided
would be calculated to satisfy the statistical number required to correct the
number of line deficiencies within the substrate. The arrangement is indicated