Browse Prior Art Database

Dynamic Memory Refresh Sequence For Asynchronous Processor

IP.com Disclosure Number: IPCOM000067844D
Original Publication Date: 1979-Oct-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Kerrigan, M Matter, PA Temple, JL [+details]

Abstract

Lost access/cycle time is avoided by guaranteeing to a processor that a forthcoming memory access operation (OP) will not be interrupted, once started, because of the need to refresh the memory. The memory sends a signal to the engine when the memory is being refreshed. If the engine is about to do a memory access operation, the engine will stop and will not start the operation until after the memory refresh is completed. If the memory is not refreshing, the engine will not stop.