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Power Dissipation Adjustment In A Read-Only Memory Disclosure Number: IPCOM000067849D
Original Publication Date: 1979-Oct-01
Included in the Prior Art Database: 2005-Feb-20

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Mollier, P Nuez, JP Rivierre, J [+details]


In a monolithic read-only memory comprising NPN transistors as storage cells, with the bases connected to word lines. the information is loaded by personalization of the master slice by forming or not the emitters of the NPN transistors, a NPN transistor with an emitter connected to a bit line representing a "one" and a NPN transistor without an emitter representing a "zero".