Adaptive Synchronization Of Processing Clocks
Original Publication Date: 1979-Oct-01
Included in the Prior Art Database: 2005-Feb-20
Referring to Fig. 1, input-output channel processor 1, used as a standard assembly part of two (or more) data processing systems, A and B, is required to operate at different cycle clocking rates in each system. Also, the central processors in these systems may operate at cycle clocking rates which may differ from each other and from the rate of processor 1. In order to minimize unproductive time in processor 1, between its requests for access to main storage 2A or 2B in the associated system and the actual servicing of the requests, the cycle clocking function in processor 1 is required to be synchronized with a timing reference derived from the cycle clock in the respective central processor 3A or 3B.