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Interleaved Multiple Speed Memory Controls With High Speed Buffer Disclosure Number: IPCOM000067902D
Original Publication Date: 1979-Oct-01
Included in the Prior Art Database: 2005-Feb-20

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Related People

Feretich, RA Sachar, HE [+details]


This memory system consists of M digits of high speed memory and NM digits of a lower speed memory, where frequently used routines are stored in the high speed memory and occasionally used routines are stored in low speed memory. There is no transfer of routines from low to high speed memory, or vice versa.