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This is a test algorithm to test serial access memory cards, where full addressing is not available.
English (United States)
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Serial Access Memory Test Method
This is a test algorithm to test serial access memory cards, where full
addressing is not available.
Each memory card 10 consists of a number of memory modules 12.
Each module consists of a number of blocks or loops 14 which are
addressable, and each loop or block 14 actually consists of a
plurality of n shift registers 16.
By a hardware pattern generator, a data pattern is generated that will result in
loading each of the shift registers 16 with a unique address. This address
consists of the following components: (1) the module address: (2) the block
address, and (3) the shift register address.
In addition, preselected patterns are written into the remaining stages of each
of the shift registers of all "0's", all l's", or alternate "0's" and "l's".
After the entire card is written, reading commences. If data from any loop is
broken, or if an addressing failure occurs, an error is indicated.
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