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With this error checking scheme writing or reading a page of n bits into or out of a data loop may begin at any position i, 0 < i < n-1. It continues end-around until bit i-1 is written or read.
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Roll Mode Error Checking Scheme
With this error checking scheme writing or reading a page of n bits into or out
of a data loop may begin at any position i, 0 < i < n-1. It continues end-around
until bit i-1 is written or read.
There are 3 M-stage shift registers in the encoder-decoder, where M is the
degree of the generator polynomial. In the following description, the generator
polynomial g(x) = 1+x/5/ + X/12/ + x/16/ of degree 16 is used for illustration.
There is a 16-bit error correcting code (ECC) check for each page. The ECC
checks are stored in an array and are fetched for error checking when data are
read from a change-coupled device (CCD).
Before writing begins at position i, 0 < i < n-1, shift registers REG 1 and REG
3 are cleared, and shift register REG 2 is set to be 100...0 (1 at the lowest-order
bit and 0's at the 15 high-order bits). As each data bit is written into the loop, the
data bit is also fed into REG 1 (Fig. 1). After each entry, REG 1 is shifted once.
For the first (n - i) entries the control signal C in REG 1 is set at 1, and for the
next i entries C is set at 0. REG 2 is shifted, without input each time a data bit is
written for the first n - i data bits. It then stops shifting while the rest of the data
bits are fed into the CCD and REG 1.
After n data bits are fed into REG 1, the contents of REG 1 and REG 2 are to
be multiplied. This is accomplished with the circuit shown in Fig. 3. The
multiplication is done sequentially in 16 shifts...