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Master/Slave Cascade Channel For Microprocessor DMA Disclosure Number: IPCOM000067921D
Original Publication Date: 1979-Oct-01
Included in the Prior Art Database: 2005-Feb-20

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Schuelka, DJ [+details]


The logic circuit of the figure illustrates the direct memory access (DMA) control of a microprocessor system with a single bus architecture, wherein a four-channel direct memory access microprocessor is expanded to control eight or more channels. The control of the bus is through two lines: bus request (BRQ) and bus grant (BGNT). To control eight channels, two identical DMA cards are used with only the system wiring being different. The circuit, found on all DMA cards used in the system, resolves bus control and priority, but is unused by the slave card when connected to a master.