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Metal Oxide Silicon Circuits On Silicon Membranes

IP.com Disclosure Number: IPCOM000067938D
Original Publication Date: 1979-Oct-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Petersen, KE [+details]

Abstract

One of the limitations in fabricating submicron structures from silicon using electron-beam lithography is the additional undesirable resist exposure due to the backscattered electrons generated in the thick substrate. It is a well-established principle that the narrowest linewidths can be written only in resist which has been deposited on very thin substrates. A logical extension is to develop a technique for fabricating transistors in thin, single-crystal silicon membranes. In addition to smaller dimensions using electron-beam exposures, such devices would be free of parasitic effects with the substrate and could easily be fully isolated from each other. These extra advantages would result in improved operating characteristics for transistors and circuits fabricated in this way.