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Bypass Selection Mechanism For Defective Chips Disclosure Number: IPCOM000068051D
Original Publication Date: 1979-Nov-01
Included in the Prior Art Database: 2005-Feb-20

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Aichelmann, FJ [+details]


A control technique for CCD (charge-coupled device) memories is described whereby loop address synchronization is achieved without a chip with a defective region having to be clocked at the select (fast) clock rate when an all good chip is substituted for it.