Browse Prior Art Database

Reduction Of Bit Line Capacitance In Memory Cells

IP.com Disclosure Number: IPCOM000068076D
Original Publication Date: 1979-Nov-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Beyer, KD Poponiak, MR [+details]

Abstract

Typical random-access memories utilize a one-transistor cell consisting of a capacitor, a gate and a drain area. The cell structure is isolated by conventional thermal SiO(2) isolation. The bit (signal) is stored in the capacitor. Information is read from the cell by opening an electronic gate and detecting a differential voltage signal that is inversely proportional to bit line capacitance. A small bit line capacitance would therefore produce a large differential voltage signal which is very desirable because it can be detected without sensitive, slow, sensing circuitry.