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Bidirectional Data Shifter

IP.com Disclosure Number: IPCOM000068085D
Original Publication Date: 1979-Nov-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Chang, DC [+details]

Abstract

The data shifter represented by Fig. 1 uses bidirectional shift stages to achieve right and left shifts. The example given is a 64-bit shifter and consists of three stages with the indicated shift amounts. Two unique features of the shifter which contribute to reductions in circuitry and delay are: 1. Utilization of bidirectionality of shift stages by combining shifts differentially as well as additively. For example, a right three shift would be performed as a left one shift followed by a right four shift. 2. A special assignment of shift weights to each of the shift (amount) control bits, which allows a bit significant decode instead of requiring a total decode of all (6) control bits.