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Guard Digit Activation During Multiply Disclosure Number: IPCOM000068086D
Original Publication Date: 1979-Nov-01
Included in the Prior Art Database: 2005-Feb-20

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Letteney, RC Levine, SR [+details]


In large data processing systems, high speed multiply can be accomplished by utilizing carry save adder trees in which a plurality of multiplier bits are decoded to present a plurality of multiplicand multiples to the input of the carry-save adder tree. For example, 64 bits of multiplier and multiplicand can be processed in eight iterations utilizing eight bits of the multiplier during each iteration, and forming eight bits of a final product.