Browse Prior Art Database

Dynamic LSSD Latch

IP.com Disclosure Number: IPCOM000068193D
Original Publication Date: 1979-Dec-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
King, KR [+details]

Abstract

The silicon area required to produce an LSSD (Level Sensitive Scan Design) latch is reduced by providing a dynamic master and a static slave. A total of three clock signals is required to operate the latch in two modes, as shown in the figure. The logic operation is provided by the combination of 0(1) to control the dynamic input device and 0(2) to control the static output device. In the scan mode, operation is controlled by 0(2) and the scan signal while 0(1) is logical zero. This implementation reduces the number of devices required for the latch by a minimum of two stages, and the required silicon area is further reduced by using a storage capacitor to replace additional FET devices.