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What is shown and described is apparatus for high speed transmission of self-clocked serial data including the generation of a pulse amplitude modulate wave using a split resistor technique.
English (United States)
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What is shown and described is apparatus for high speed transmission of
self-clocked serial data including the generation of a pulse amplitude modulate
wave using a split resistor technique.
Fig. 1 shows a block diagram of the data interface, and Fig. 2 shows a
simplified schematic. Data enters the interface through a buffer. From the buffer
the data is transferred to a shift register, then read out as a serial string. From
the serializer, the data is pulse amplitude modulated and transmitted over a
coaxial line. Data enters the receiver where the data and clock are separated.
Data and clocks are then deserialized and distributed to other machine logic.
The buffer is a 12-bit register that serves as a hold point for the data input.
The serializer is a 12-bit shift register with the capability of parallel and serial
load. The shift register parallel loads the data word and shifts in a stream of "1"
bits as the data word is shifted out to the transmitter. When the register is full of
"1" bits, the shifting is complete and a STOP command is issued. The next data
word can now be loaded. The first data bit is separated from the other 11 bits
and its position in the buffer SR is set to zero in order to guarantee the shift
register does not have all "1's" after data load. This holds the STOP signal
inactive until the last bit is transferred. The first bit is routed to the transmitter
directly from the buffer.
The transmitter is four open collector NAND gates with a 60 ma drive
capability. The 60 ma driver is required as the receivers are terminated in the