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Decoding of instructions from the instruction register many times causes excess delay before actions required by the instructions are performed.
English (United States)
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Microprocessor Performance Enhancement by Pre-Decoding
Decoding of instructions from the instruction register many times causes
excess delay before actions required by the instructions are performed.
At the beginning of each instruction to be executed, the instruction register is
generally set and information needed to execute the instruction (arithmetic
function, register addresses, branch conditions, etc.) is decoded from the
instruction register before execution can proceed. The source of the address for
the next memory cycle must be determined since the address will be different for
a Branch instruction, a Load Data instruction or other instructions in which the
next sequential address is required. In addition, for arithmetic instructions the
local store address must be determined and accessing of data begun.
In a microprocessor, the instruction register may have been set during the
execution of the previous Data Store instruction and the decoding of the
instruction from the instruction register that is required does not incur any
additional delay. For all other instructions, however, there is a considerable time
required for the contents of the instruction register to be reset and set with the
new instruction information. Powering up the instruction register and decoding
the required branch and addressing information takes additional delay, and
several hundred nanoseconds may be lost until the proper decode is guaranteed.
Since the source of data set into the instruction register is from the storage
data bus which is generally available prior to the time the instruction register is
loaded, considerable time can be saved if the actions that need to be perfor...