Browse Prior Art Database

Logic Partitioning Method

IP.com Disclosure Number: IPCOM000068237D
Original Publication Date: 1979-Dec-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Pivnichny, JR [+details]

Abstract

STATEMENT OF PROBLEM: Several MSI (medium scale integration) chips (10-100 circuits) are to be more densely integrated into two LSI (large- scale integration) chips (100-1000 circuits). Because the LSI chips have limitations on I/O pads, it is necessary to partition the MSI chip logic into two parts in such a way as to minimize the number of I/O connections needed to communicate between the two LSI chips. SOLUTION: The method of making this partition is discussed below. From combination theory the number of possible solutions is: P = (Image Omitted) n - number of MSI chips r - number of MSI chips on first LSI chip. Each possible partitioning solution can be encoded as an n-bit binary word with r "ones" and (n-r) "zeros", wherein a "one" denotes partitioning onto the first LSI chip.