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Improved Shifting And Packing Circuitry Disclosure Number: IPCOM000068240D
Original Publication Date: 1979-Dec-01
Included in the Prior Art Database: 2005-Feb-20

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Povlick, TR [+details]


U.S. Patent 4,141,005 shows a circuit for shifting and packing/unpacking data. The circuit shown in this patent includes two cascaded stages. Each integrated circuit chip includes circuitry for shifting 16 bits of data. As shown in the patent, a bidirectional storage bus connects to each chip requiring 16 pins for the input/output of data. Similar circuitry could be used with separate input and separate output data busses. However, in such a situation, 32 I/O pins would be required for data input and output to each chip. In some applications, it is not possible to assign 32 pins for this function.