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Double Polysilicon MTL Structure

IP.com Disclosure Number: IPCOM000068274D
Original Publication Date: 1979-Dec-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Berger, HH Thiel, KP Wiedmann, SK [+details]

Abstract

In merged transistor logic (MTL) transistor structures, the base and (top) collector contacts are made of P+ and N+ doped polysilicon. Where these oppositely doped polysilicon layers overlap or abut, a diode is formed which is series-connected between an output (collector) and an input (base) of another MTL structure. In this manner, the advantages inherent in the use of polysilicon technology are combined with the reduced logic swing obtainable by the series diode, which significantly improves the speed and the power delay product.