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Layout Image For Merged Transistor Logic

IP.com Disclosure Number: IPCOM000068357D
Original Publication Date: 1979-Dec-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Feth, GC Wiedmann, SK [+details]

Abstract

For practical application of MTL (merged-transistor logic) especially in VLSI (very large-scale integrated) circuits, two conflicting requirements must be met. One requirement is that the base resistance of the output npn transistors be kept small to limit the voltage drop laterally across the base regions so as to assure sufficient collector current at the collector which is farthest from the current source, i.e., from the collector of the pnp transistor (a functionality requirement), and at the same time the area of the junctions must be kept small in order to avoid excessive charge storage, capacitive loading and emitter current, which are proportional to the junction area (power-performance problem).