Browse Prior Art Database

Josephson Power System Design

IP.com Disclosure Number: IPCOM000068362D
Original Publication Date: 1979-Dec-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Arnett, PC Herrell, DJ [+details]

Abstract

The requirements on a power system for Josephson interferometer latching logic circuits are that the regulated power signal must be supplied with a low skew throughout the system (less than about 5% of the logic cycle) while operating at high frequencies (around a 2 ns logic cycle) and keeping system currents low (less than about 0.5 A). The design techniques which accomplish these objectives are illustrated in the example of figure 1. Low skew is obtained through the use of balanced parallel power distribution from transformer secondaries. Currents are kept low by multiturn transformer primaries. The presence of a standing wave resonance along the transformer primaries is countered by only connecting two transformers in series and by interleaving the connection of the primary turns of these transformers.