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Process For Making Self-Aligned Deep And Shallow Isolation Trenches For Transistors

IP.com Disclosure Number: IPCOM000068396D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Cavaliere, JR Ho, AP Horng, CT Konian, RR [+details]

Abstract

Isolation of the transistor in Fig. 1 is achieved by the oxide-filled isolation trenches 1 and 2, whereby deep trench 1 and shallow trench 2 are self-aligned relative to each other.