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Isolation of the transistor in Fig. 1 is achieved by the oxide-filled isolation trenches 1 and 2, whereby deep trench 1 and shallow trench 2 are self-aligned relative to each other.
English (United States)
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Process For Making Self-Aligned Deep And Shallow Isolation Trenches For
Isolation of the transistor in Fig. 1 is achieved by the oxide-filled isolation
trenches 1 and 2, whereby deep trench 1 and shallow trench 2 are self-aligned
relative to each other.
In Fig. 2, N+ subcollector 3 is placed in P- substrate 4 and epi layer 5 and
CVD (chemical vapor deposited) oxide 6 (approximately 0.8 (mu) m) are
deposited on the substrate. A resist masking layer 7 is formed on the oxide and
patterned to expose the deep and shallow trench areas shown in Fig. 1.
CVD oxide 6 is etched away in the unmasked areas, and resist layer 7 is
removed. The exposed silicon is reactively ion etched to a depth of about 1 (mu)
m, while the remaining CVD oxide thickness is reduced to about 0.7 (mu) m, as
shown in Fig. 3.
A second CVD oxide layer 8 (about 0.7 (mu) m) is deposited over the
structure, and a second resist mask 9 is formed, as shown in Fig. 4 to cover only
the shallow trench area. The CVD oxide 8 exposed by mask 9 is etched away
using an end-point detector to stop the etching action when the silicon in the
deep trench area 10 is exposed.
Resist 9 is removed, and the structure is reactively ion etched to remove an
additional 3 (mu) m of silicon in area 10, while the remaining CVD oxide outside
the area 10 is reduced to a thickness no less than about 0.2 (mu) m. CVD oxide
11 (about 750 angstroms) is deposited to protect the sidewalls of the deep trench
against boron implant...