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It is known that for maintaining stored information, dynamically operated semiconductor storages require refresh pulses which have to be applied in refresh cycles at particular predetermined times.
English (United States)
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Increasing The Performance Of Computers By Shifting The Refresh Cycles
Of Internal Storage
It is known that for maintaining stored information, dynamically operated
semiconductor storages require refresh pulses which have to be applied in
refresh cycles at particular predetermined times.
As no read/write operation can be performed during refresh cycles, such
cycles decrease the performance of the computer.
The illustrated circuit uses the principle of reducing the time between
successive refresh cycles, so that they can be slightly delayed, if necessary,
without losing the stored information. For this purpose, the illustrated circuit
decodes the micro-instructions, which effect storage accesses, and blocks the
execution of a refresh cycle by means of its "PU Storage Access Op Code"
signals. It is only when a PU internal micro-instruction is executed after such
storage related micro-instructions that the refresh cycle thus delayed is executed,
without delaying the PU internal micro-instruction.
As a result, the refresh cycles become transparent to the processor PU. The
processor performance in general and the critical microprogram phases in
particular are neither reduced nor interfered with by the refresh cycles. The
illustrated circuit is also capable of handling exceptional cases where the
sequence of storage-related micro-instructions is of such duration that it exceeds
the delay tolerance of the refresh cycle. In such cases, whose occurrence can
be reduced by suitable programming steps, count ring TII forces a refresh cycle.
Instead of controlling the refresh cycles as a function of the storage-related
micro-instructions, they can also be made dependent on other processor
The principal part of the illustrated circuit arrangement is count ring TI in
which count ring TII is integrated. Thi...