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This latch can function as a clocked, logically hazard-free polarityhold latch or a clocked, Set-Reset latch.
English (United States)
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This latch can function as a clocked, logically hazard-free polarityhold latch
or a clocked, Set-Reset latch.
Fig. 1 shows a latch which, with four gates, has a minimal implementation. If
R is either held or left to float "positive" (noncontrolling value for AI gate), the
latch behaves like a clocked polarity hold latch in which the data stored, when the
clock is turned "ON" is the "AND" of D1 and D2. If D2 is held positive and D1 is
used as the Set input and R as the Reset input, then as the table in Fig. 1 shows,
the output L represents the output of a Set dominant clocked, Set Reset latch. If
D1 acts as the Reset input and R as the the output of a Reset dominant, clocked,
In Fig. 2, an extra gate is added to provide a scan capability to the latch, so
that it can function as the L1 latch in a Shift Register Latch.
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