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Interface Freeze Mechanism Disclosure Number: IPCOM000068511D
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Feb-20

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Moyer, JT [+details]


Coupling circuits are described which enable logic circuitry using a level sensitive scan design (LSSD) to be coupled to logic circuitry not using LSSD, whereby a scan-in or scan-out operation may be performed on the LSSD logic circuitry without affecting the non-LSSD logic circuitry.