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The illustrated structure provides an engineering hardware modeling capability for large-scale integrated semiconductor circuits.
English (United States)
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Large Scale Integration Modeling Technique
The illustrated structure provides an engineering hardware modeling
capability for large-scale integrated semiconductor circuits.
In the fabrication of semiconductor integrated circuits, a plurality of identical
unit cells 12 are formed on a semiconductor substrate 10. Each unit cell 12
consists of a plurality of electronic components, such as transistors, diodes and
resistors, to form unit cells, such as AND gates, when selectively interconnected
via a first level metallization. It is further known to interconnect such unit cells to
form higher level functional units, such as counters, such higher level logic units
being also referred to as macros. These macros are formed by selectively
interconnecting the unit cells by a second level of metallization, forming various
macros in selected regions of the semiconductor, as illustrated by macro M1, M2,
M3, and M4 in the figure. The second level of metallization is also used to
interconnect the various macros with each other, as illustrated by the horizontal
metallization lines in the figure.
The vertical metallization lines in the figure, which represent a third level of
metallization, form a grid with the horizontal metallization lines and permit
selected interconnection of the second and third levels by using a cross point via
connection. This extremely dense configuration is adapted for hardware
modeling merely by the selective interconnection of the second level (horizon...