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Disclosed is circuitry contained on a dynamic memory chip which determines the appropriate time, and triggers circuitry for refreshing the dynamic memory chip.
English (United States)
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Dynamic Memory Refresh Detection and Triggering Circuit
Disclosed is circuitry contained on a dynamic memory chip which determines
the appropriate time, and triggers circuitry for refreshing the dynamic memory
Features: 1. Provides on-chip detection (and triggering) of the refresh
requirements of an amoeba-type bipolar dynamic memory, hence,
minimizing off-chip interface requirements. 2. The charge monitoring
cell is a modified memory cell with
an area enhancement to provide slightly more leakage
than regular memory cells. 3. The detection and triggering circuitry is subject to the same
process, temperature, power supply, etc., variations as the
storage cells, and thus, its condition will track the storage
cells. Hence, the availability of the memory is optimized
rather than being determined by the worst-case operating
conditions and the worst-case chip contained within the total
memory. In addition, aging tracking is provided. 4. The use of the double emitter of T1 provides a beta
the leakage which, along with the area enhancement,
provides about a
factor of 100-200 leakage multiplier. A
factor of 100 is expected
to cover a six sigma process spread of leakage. 5. The emitter-base junctions E1 and E2 are utilized to
place a stress
across emitter junction E1, and it allows control of the stress
through adjusting VR; hence, an off-chip screening and refresh
adjust is provided to allow yield enhancement, if so desired. 6. The SCR action provided by device T2, generates a ref...