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Top Line Selection Circuit a Memory Cell Disclosure Number: IPCOM000068562D
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Feb-20

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Boudon, G Denis, B Grandguillot, M [+details]


Described is a means for minimizing the effect of power supply voltage variations and the integrated component tolerances on the voltage levels of a read/write array top line. The main advantage of top-line level control is memory cell stability, that is a constant cell current Ic.