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Storage Cell Disturb Test

IP.com Disclosure Number: IPCOM000068571D
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Heubert, K Klein, W Najmann, K Wernicke, F Wiedmann, SK [+details]

Abstract

To ensure that the storage cells of highly integrated bipolar semiconductor storage do not disturb each other, specific test procedures have to be applied. The procedural steps for verifying that no cell is affected by another during writing are described below: 1. Binary value "0" is written into all storage cells. 2. A "1" is written into ~ cell (cell A), line 1. 3. The right-hand neighbor (cell C) of cell A is read, half-selecting cell A. In the subsequent phase of the read cycle, during which the cell nodes of cell A resume their standby potential, cell A is highly susceptive to spurious effects, to which it may be subjected via bit-line pair B0, B1, column 1.