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Tolerance Trimming of Electrical Data of LSI Semiconductor Circuits

IP.com Disclosure Number: IPCOM000068578D
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Remshardt, H Schettler, H Schumacher, H Zuehlke, R [+details]

Abstract

For the tolerance trimming of the electrical data of large-scale integration (LSI) semiconductor circuits, such as power, delay, voltage and current levels, and access time, an additional circuit is provided on the semiconductor chip. It contains circuit elements such as resistors, the values of which can be altered and via which the electrical data of the semiconductor chip can be influenced. In a test following a metallization step a reference quantity on the chip is measured and compared with a nominal value. Subsequently, the circuit elements on the chip are automatically altered by means of a program-controlled tester. The circuit elements can be altered iteratively, i.e.