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An off-chip driver latch performs the function of latching signals from a timing shift register and propagating the signals from the logic chip without requiring an off-chip driver device.
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Off Chip Driver Latch
An off-chip driver latch performs the function of latching signals from a timing
shift register and propagating the signals from the logic chip without requiring an
off-chip driver device.
The timing signal is applied to terminal P SET of field-effect transistor (FET)
device 11 which exhibits a high W/L ratio (e.g., 32). Assuming Initially that node
N OUT is down and node N1 is high, the latch circuit comprising devices 13-19
will be in its reset state. When the signal P SET is taken high, device 11 turns
on, and the latch is set. Once the P SET signal drops, device 11 turns off, and
the latch remains set, with device 13 providing drive for the leakage current on
the output node. In order to reset the latch, P RESET is taken high, turning on
device 21. The output voltage fall time is controlled by the W/L ratio of device 21. The test input is used to force the output high during the functional testing of
Since the W/L ratio of device 11 is high, it can drive an output capacitance of
25 pf in about 100 ns with a minimum amount of power dissipation. Since the
W/L ratio of device 13 is low (e.g., .5), minimal power is dissipated during the
remainder of the off-chip drive.
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